GTW 2007 - Call for Participation

CALL FOR PARTICIPATION

Scope -- Program Overview -- Venue -- Workshop Registration -- Advance Program -- More Information -- Committees

Scope

Electronic circuits running in the multi-GHz clock range and/or including I/O capable of multi-Gbps data rates are now increasingly common. The characterization, production testing, and diagnosis of such circuits pose significant challenges. GTW’07 is a workshop that specifically addresses problems and solutions related to ATE and test methodologies concerning issues that arise with circuits running at such GHz clock and/or Gbps data rates. GTW'07 offers a focused forum for experts, as well as for members of the community with a particular interest in this rapidly expanding specialized field. GTW’07 is sponsored by the IEEE Computer Society Test Technology Technical Council.

Program Overview

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A high-quality programme, built from the contributions submitted to both GTW and IMSTW, has been prepared. This joint program comprises seven regular and two poster sessions, with in total thirty five presentations, covering the areas of analogue, mixed-signal, RF, high-speed IO, MEMS, and board test. A panel session on GHz/Gbps testing will present and discuss issues involved in testing electronic circuits running in the multi-GHz clock range and/or including I/O capable of multi-Gbps data rates. Three invited key-note speeches will address the critical test topics of using analogue approaches for testing low-power digital IC’s, GHz/Gbps testing, and the challenges of MEMS testing.

The Venue

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The Workshop will take place in the Novotel Vermar Hotel in the city of Póvoa de Varzim. Located near the airport, and with easy access to downtown Porto, Póvoa de Varzim lies in a sandy coastal plain in the northwest region of the country known as Costa Verde. Inland, there are several historic and interesting cities, towns and villages that fascinate the passing tourist and bear testimony of the ancient beginnings of modern Portugal. The social programme includes a visit to Guimarães, the first capital of Portugal in the twelfth century. Its Historic Centre was awarded the status of World Heritage of Humankind by UNESCO in 2001.

Workshop Registration

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The registration for the joint IMSTW/GTW’07 event is now open. Advance registrations can be received until the 25th of May, 2007. More details can be found on the website at www.fe.up.pt/gtw07/registration.htm

Advance Program

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Monday -- Tuesday -- Wednesday

June 18 , 2007 (Monday)

9:00 AM - 10:00 AM	Opening Session
9:00 - 9:10	Welcome Address
9:10 - 10:00	Invited Talk 1 – Testing Low Power Digital IC's May Require Mixed-Signal Test Solutions Joan Figueras, Universitat Politècnica de Catalunya

10:00 AM - 10:20 AM	Poster Session 1
P1.1	Wavelet – Neural Network to Analog Parametric Fault Circuit Location Damian Grzechca, Silesian University of Technology, Poland
P1.2	Implementing a Tuning Algorithm for Continuous-time Filters in a Digital Environment Gianvito Matarrese, Cristoforo Marzocca, Francesco Corsi, Dipartimento di Elettrotecnica ed Elettronica - Politecnico di Bari, Italy
P1.3	Estimation and Adaptive Correction of PA’s Nonlinearities José Machado da Silva, Pedro Mota, John Long, INESC Porto, Universidade do Porto, Portugal, TUDelft, The Netherlands

10:20 AM - 10:50 AM BREAK POSTER SESSION 1

10:50 AM - 12:30 PM	Session 1 – Analogue Testing
S1.1	Functional Test Compaction by Statistical Modelling of Analogue Circuits Nourredine Akkouche, Ahcène Bounceur, Salvador Mir, Emmanuel Simeu, TIMA Laboratory, France
S1.2	Testing SET Effects in a CMOS Operational Amplifier Jose Huertas, John Espinosa, Gloria Huertas, Jaime Velasco-Medina, Raoul Velazco, Universidad de Sevilla, Spain, Universidad del Valle, Colombia, IMSE-CNM, Spain, TIMA Laboratory, France
S1.3	A Tool for Single Fault Diagnosis in Linear Analog Circuits José Augusto, Carlos Almeida, Universidade de Lisboa - FCUL and INESC -ID, IST-UTL and Inesc-ID, Universidade de Lisboa - FCUL, Dep. de Física, Portugal
S1.4	Impact of Circuit Parameter Derivative Calculation on Estimation of Statistical Variables for Analog Fault Detectability Evaluation Alkiviades Hatzopoulos, Dimitrios Papakostas, Aristotle University of Thessaloniki, A.T.E.I.Th., Greece

12:30 PM - 2:00 PM LUNCH

2:00 PM - 3:15 PM	Session 2 – Mixed-Signal Test
S2.1	Noise-insensitive BIST to Measure Small Phase Delays Stephen Sunter, Aubin Roy, LogicVision, Inc., USA
S2.2	Gaps in Timing Margining Test for Serial Interfaces: A Case Study Anne Meixner, Dongwoo Hong, Benoit Provost, Intel, USA, University of California, Santa Barbara, USA
S2.3	A Built-in Methodology for Resemblance Gathering in RKII Networks Manuel Cândido Santos, Vitor Grade Tavares, José Machado da Silva, Sebastian Tabarce, FEUP/DEEC - University of Porto, INESC Porto, Portugal

3:15 PM - 3:45 PM BREAK

3:45 PM - 5:25 PM	Session 3 – RF Testing
S3.1	Optimization of Behavioral Level Design Validation Test Bench for Production Testing of AMS & RF SoCs Yves Joannon, LCIS INPG, France
S3.2	Using Signal Envelope Detection for RF MEMS Switch Testing E. Simeu, H. N. Nguyen, P. Cauvet, S. Mir, L. Rufer, R. Khereddine, TIMA Laboratory, NXP Semiconductors, France
S3.3	Built-In Test of RF Receivers Using RF Amplitude Detectors Chaoming Zhang, Ranjit Gharpurey, Jacob Abraham, University of Texas at Austin, USA
S3.4	Built-in Test Enabled Diagnosis and Tuning of RF Transmitter Systems Rajarajan Senguttuvan, Abhijit Chatterjee, Vishwanath Natarajan, Georgia Institute of Technology, USA

6:00 PM WELCOME RECEPTION

June 19, 2007 (Tuesday)

9:00 AM - 9:40 AM	Invited Talk 2 – Multi-GHz and Multi-Gbps Testing Issues
	To be defined

9:40 AM - 10:20 AM	Session 4 – Board and System Level Test
S4.1	Embedded Test Controller for Board and System Level Remote Testing Jari Hannu, Tuomas Happonen, Markku Moilanen, University of Oulu, Finland
S4.2	A Built-in Debugger for 1149.4 Circuits Manuel Felgueiras, Gustavo Alves, José Ferreira, ISEP, University of Porto, Portugal

10:20 AM - 10:50 AM BREAK

10:50 AM - 12:30 PM	Session 5 – GHz/Gbps Testing
S5.1	Testing SerDes ICs Beyond 4 Gbps – New Priorities Stephen Sunter, Aubin Roy, LogicVision, Inc., USA
S5.2	A Novel Built-in Test Technique for Phase/Frequency Modulated RF Transmitters Hyun Choi, Donghoon Han, Abhijit Chatterjee, Georgia Institute of Technology, Atlanta, USA
S5.3	Design and Implementation of Low Noise and High Speed Multilayer Test Board with High Performance 3D-EBG Structure Kijae Song, Samsung Electronics, Koreay
S5.4	MEMs Switches and SiGe Logic for Multi-GHz Loopback Testing David C. Keezer, Dany Minier, Patrice Ducharme, Doris Viens, Greg Flynn, John Mckillop, Georgia Institute of Technology, Atlanta, USA, IBM, Bromont, Canada, TeraVicta, Austin, USA

12:30 PM - 2:00 PM LUNCH

2:00 PM - 3:45 PM	Panel Discussion
	Organizer: Stephen Sunter, LogicVision, USA

4:00 PM SOCIAL EVENT

June 20, 2007 (Wednesday)

9:00 AM - 9:40 AM	Invited Talk 3 - The Challenges of MEMS Testing
	Shawn Blanton, Carnegie Mellon University

9:40 AM - 10:20 AM	Poster Session 2
P2.1	A Novel Binary Search Method for Characterizing Hysteresis Featured in Integrated Circuits Weishu Wu, Texas Instruments
P2.2	Mixed-signal Design of Dynamic Delay Buffers to Improve Tolerance to Power Supply and Temperature Variations Jorge Semião, João Paulo Teixeira, Isabel Teixeira, Fabian Vargas, Juan J. Rodriguez-Andina, Judit Freijedo, Escola Superior de Tecnologia - Universidade do Algarve, IST/INESC-ID, Portugal, Catholic University - PUCRS, Brazil, University of Vigo, Spain
P2.3	Considerations for FPGA Integration into the ATE Device Interface Board Ian Grout, Thomas Oshea, Jeffrey Ryan, University of Limerick, Ireland
P2.4	Layout-Oriented Fault Analysis for DRAM Design Components Martin Versen, Jelena Kneževic, Sergio Montoya, Torsten Coym, Wolfgang Vermeiren, Bernd Straube, Qimonda AG, Fraunhofer Inst. für Int. Schaltungen (IIS), Germany
P2.5	Accurate Linearity Testing of A/D Converters in the Presence of Ground Bounce Noise Shalabh Goyal, Abhijit Chatterjee, Georgia Institute of Technology, USA
P2.6	White Noise Signal Generator for ADC Testing Josef Vedral, CTU FEE Prague, Czech Republic

10:20 AM - 10:50 AM BREAK POSTER SESSION 2

10:50 AM - 12:30 PM	Session 6 – MEMS Testing
S6.1	Inductive Fault Analysis for DNA Sensor Arrays Daniela de Venuto, Politecnico di Bari, Italy
S6.2	Self-Testing of Micro-Electrode Array Implemented as a Bio-Sensor Hongyuan Liu, Lancaster University, United Kingdom
S6.3	Capacitive MEMS Accelerometers Testing Mechanism for Auto-calibration and Long-term Diagnostics Luís Rocha, Lukas Mol, Edmond Cretu, Reinoud Wolffenbuttel, José Machado da Silva, Faculdade de Engenharia da Universidade do Porto, Portugal, Delft University of Technology, The Netherlands, University of British Columbia, Canada, INESC Porto, Portugal
S6.4	A Fault-Tolerant MEF Peptide Synthesizer Using Sense-Electrode Xiao Zhang, Hans Kerkhoff, Frédérick Mailly, Pascal Nouet, Hongyuan Liu, Andrew Richardson, TDT, CTIT, University of Twente, The Netherlands, LIRMM, France, Lancaster University, United Kingdom

12:30 PM - 2:00 PM LUNCH

2:00 PM - 4:05 PM	Session 7 – ADC Test
S7.1	A Simple Method for Linearity Testing of ADCs Using Nonlinear Test Stimuli Esa Korhonen, Juha Kostamovaara, University of Oulu, Electronics Laboratory, Finland
S7.2	Postprocessing Measurement Data---Are You Using the Correct Algorithm? Carsten Wegener, Infineon Technologies AG, Germany
S7.3	Fully-Efficient ADC Test Technique for ATE with Low Resolution Arbitrary Wave Generators Vincent Kerzérho, Philippe Cauvet, Serge Bernard, Florence Azäis, Michel Renovell, Mariane Comte, NXP, LIRMM, LIRMM, France
S7.4	Simple Evaluation of the Non-linearity Signature of an ADC Using a Spectral Approach Eduardo Peralias, M. Angeles Jalon, Adoracion Rueda, IMSE-CNM, Universidad de Sevilla, Spain
S7.5	A Methodology for Structural Test of Folded ADCs Roman Mozuelos, Yolanda Lechuga, Mar Martinez, Salvador Bracho, University of Cantabria, Spain

4:05 PM - 4:20 PM CLOSING SESSION

More Information

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General Information
David Keezer
Georgia Institute of Technology
Atlanta, Georgia 30332
Tel: 1 (404) 894-4741
E-mail: dkeezer@ece.gatech.edu

Program Information
Abhijit Chatterjee
Georgia Institute of Technology
Atlanta, Georgia 30332
Tel: 1 (404) 894-4741
E-mail : chat@ee.gatech.edu

W. R. Eisenstadt
University of Florida
Gainesville, FL 32611
Tel: 1 (352) 392-2543
E-mail: wre@tec.ufl.edu

Local Information
José Machado da Silva
Faculty of Engineering, University of Porto
4200-465 Porto, Portugal
Tel.: +351 225081796
E-mail: jms@fe.up.pt

Committees

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General Chair
D. Keezer, Georgia Tech., USA

Local Chair
J. Machado da Silva, U. Porto, Portugal

Program Co-Chairs
A. Chatterjee, Gerogia Tech, USA
W. R. Eisenstadt, U. Florida, USA

Publicity Chair
D. Gizopoulos, U. Piraeus, Greece

Publications Chair
Vitor G. Tavares, U. Porto, Portugal

PROGRAM COMMITTEE

M. A. d’Abreu, Sun Microsystems
J. A. Abraham, UT Austin
R. Aitken, Artisan
K. Arabi, PMC-Sierra
Y. Cai, Agere
T. Cheng, UCSB
A. Crouch, Inovys
W. R. Eisenstadt, U. Florida
J. Figueras, U. Politecnic Catalunya
C. Force, Texas Instruments
H. Haggag, National Semiconductor
M. Li, Wavecrest
S.-I. Liu, National Taiwan U.
W. Maichen, Teradyne
W. Mann, SWTW
A. Meixner, Intel
M. Omana, U. Bologna
S. Ozev, Duke U.
G. Roberts, McGill U.
M. Slamani, IBM
M. Soma, U. Washington
L. Song, Teradyne
S. Sunter, LogicVision
T. Yamaguchi, Advantest
J. Moreira, Verigy
M. Howieson, Thin Film Technology

Ex-Officio
A. Ivanov, U. British Columbia, Canada

Liaisons
North American Liason
S. Sunter, LogicVision

Local Organization
Finance: J. C. Ferreira
Audiovisuals: A. J. Araújo
Local information: J. Martins Ferreira
Industry liaisons: J. S. Matos

Faculty of Engineering, U. Porto
4200-465 Porto, Portugal
Tel.: +351 225081502
Fax: +351 225081443
E-mail: jmf@fe.up.pt

For more information, visit us on the web at: http://www.fe.up.pt/gtw07

The 3rd IEEE International GHz/Gbps Test Workshop (GTW’07) is sponsored by the Institute of Electrical and Electronics Engineers (IEEE) Computer Society's Test Technology Technical Council (TTTC).